Posted in: Other in Austria | Posted: |
Digital IC Design and Verification Engineer(s) - Austria
Our specialist semiconductor client is seeking to hire experienced Digital IC Design and IC Verification Engineers to work in their design centre in Austria.
Our ideal candidate(s) have the following experience:
Minimum of 2 years ASIC design / verification experience.
In depth knowledge experience of SystemVerilog and/or VHDL
Experience in verification of designs using UVM.
Most of the following
Experience of RTL design or verification
Experience in Constrained Random simulation
Experience in low power IC verification
Experienced in block level IC verification
Experience in Functional verification e.g. Synopsys VCS, Cadence Incisive - NCSim
Good scripting skills in Python, TCL and/or Perl
Experience in multicore Logic simulation e.g. XCelium
Able to work alone and in a team
Professional English language competence
Willingness to travel internationally
Able to work interculturally with design teams and customers in multiple locations and time zones.
Candidates should be eligible to work in the EU, and have excellent English language competence
